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PRELIMINARY DATA SHEET
256MB DDR SDRAM SO-DIMM
EBD26UC6AKSA-E (32M words x 64 bits, 2 Ranks)
Description
The EBD26UC6AKSA is 32M words x 64 bits, 2 ranks Double Data Rate (DDR) SDRAM Small Outline Dual In-line Memory Module, mounting 8 pieces of 256M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
* 200-pin socket type small outline dual in line memory module (SO-DIMM) PCB height: 31.75mm Lead pitch: 0.6mm Lead-free * 2.5V power supply * Data rate: 333Mbps/266Mbps (max.) * 2.5 V (SSTL_2 compatible) I/O * Double Data Rate architecture; two data transfers per clock cycle * Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver * Data inputs, outputs and DM are synchronized with DQS * 4 internal banks for concurrent operation (Components) * DQS is edge aligned with data for READs; center aligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data referenced to both edges of DQS * Data mask (DM) for write data * Auto precharge option for each burst access * Programmable burst length: 2, 4, 8 * Programmable /CAS latency (CL): 2, 2.5 * Refresh cycles: (8192 refresh cycles /64ms) 7.8s maximum average periodic refresh interval * 2 variations of refresh Auto refresh Self refresh
Document No. E0605E10 (Ver. 1.0) Date Published November 2004 (K) Japan URL: http://www.elpida.com Elpida Memory , Inc. 2004
EBD26UC6AKSA-E
Ordering Information
Data rate Mbps (max.) 333 266 266 Component JEDEC speed bin (CL-tRCD-tRP) DDR333B (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3) Contact pad
Part number EBD26UC6AKSA-6B-E EBD26UC6AKSA-7A-E EBD26UC6AKSA-7B-E
Package (lead-free)
Mounted devices EDD2516AKTA-6B-E EDD2516AKTA-6B/7A-E EDD2516AKTA-6B/7A/7B-E
200-pin SO-DIMM Gold
Pin Configurations
Front side 1 pin 39 pin 41 pin 199 pin
2 pin
40 pin 42 pin Back side
200 pin
Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 101 103 105
Pin name VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 A9 VSS A7
Pin No. 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 151 153 155
Pin name VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD NC NC VSS NC NC VDD NC NC VSS CK2 /CK2 VDD CKE1 NC A12 DQ42 DQ43 VDD
Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 102 104 106
Pin name VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 A8 VSS A6
Pin No. 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 152 154 156
Pin name VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD NC NC VSS NC NC VDD NC NC VSS VSS VDD VDD CKE0 NC A11 DQ46 DQ47 VDD
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
Pin No. 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Pin name A5 A3 A1 VDD A10/AP BA0 /WE /CS0 NC VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS Pin No. 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Pin name VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID Pin No. 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Pin name A4 A2 A0 VDD BA1 /RAS /CAS /CS1 NC VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS Pin No. 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Pin name /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 NC
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
Pin Description
Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 to CK2 /CK0 to /CK2 DQS0 to DQS7 DM0 to DM7 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS VDDID NC Function Address input Row address Column address Data input/output Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground VDD identification flag No connection A0 to A12 A0 to A8
Bank select address
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
Serial PD Matrix
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM ranks Module data width Module data width continuation DDR SDRAM cycle time, CL = X -6B -7A, -7B 10 SDRAM access from clock (tAC) -6B -7A, -7B 11 12 13 14 15 16 17 18 19 20 21 22 23 DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time at CL = X -0.5 -6B, -7A -7B 24 Maximum data access time (tAC) from clock at CL = X -0.5 -6B -7A, -7B 25 to 26 27 Minimum row precharge time (tRP) -6B -7A, -7B 28 Bit7 1 0 0 0 0 0 0 0 Bit6 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 0 0 Bit5 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 1 Bit4 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 1 Bit3 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 Bit2 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0 1 Bit1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 Hex value 80H 08H 07H 0DH 09H 02H 40H 00H 04H 60H 75H 70H 75H 00H 82H 10H 00H 01H 0EH 04H 0CH 01H 02H 20H C0H 75H A0H 70H 75H 00H 48H 50H 30H 3CH 18ns 20ns 12ns 15ns 0.7ns
*1
Comments 128 bytes 256 bytes DDR SDRAM 13 9 2 64 bits 0 SSTL2 CL = 2.5*
1
Voltage interface level of this assembly 0 0 0 0 0 0 1 0 0 0 0 0
0.7ns
*1
0.75ns None
*1
7.8s Self refresh x 16 Not used 1 CLK 2,4,8 4 2, 2.5 0 1 Unbuffered VDD 0.2V CL = 2*
1
SDRAM device attributes: /CAS latency 0 0 0 0 1 0 1 0 0 0 0 0
0.75ns*
1
Minimum row active to row active delay (tRRD) 0 -6B -7A, -7B 0
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
Byte No. Function described 29 Minimum /RAS to /CAS delay (tRCD) -6B -7A, -7B 30 Minimum active to precharge time (tRAS) -6B -7A, -7B 31 32 Module rank density Address and command setup time before clock (tIS) -6B -7A, -7B 33 Address and command hold time after clock (tIH) -6B -7A, -7B 34 Bit7 0 0 0 0 0 0 1 0 1 Bit6 1 1 0 0 0 1 0 1 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 0 1 1 1 0 x 1 1 1 Bit5 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 0 1 0 0 1 1 0 1 1 0 x 0 0 0 Bit4 0 1 0 0 0 1 1 1 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0 1 1 0 x 0 0 0 Bit3 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 1 0 1 1 1 0 x 0 0 0 Bit2 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 0 0 0 0 1 1 1 0 x 1 0 1 Bit1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 1 1 0 x 0 1 0 Bit0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 1 1 0 0 x 1 0 0 Hex value 48H 50H 2AH 2DH 20H 75H 90H 75H 90H 45H 50H 45H 50H 00H 3CH 44H 48H 4BH 30H 2DH 32H 55H 75H 00H 00H E8H A2H CDH 7FH FEH 00H xx 45H 42H 44H (ASCII-8bit code) E B D Continuation code Elpida Memory Comments 18ns 20ns 42ns 45ns 128M bytes 0.75ns 0.9ns
*1
*1
0.75ns 0.9ns
*1
*1
Data input setup time before clock (tDS) 0 -6B -7A, -7B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 x 0 0 0 Data input hold time after clock (tDH) -6B -7A, -7B Superset information Active command period (tRC) -6B -7A, -7B Auto refresh to active/ Auto refresh command cycle (tRFC) -6B -7A, -7B SDRAM tCK cycle max. (tCK max.) Dout to DQS skew -6B -7A, -7B Data hold skew (tQHS) -6B -7A, -7B Superset information SPD Revision Checksum for bytes 0 to 62 -6B -7A -7B
0.45ns 0.5ns
*1
*1
35
0.45ns 0.5ns
*1
*1
36 to 40 41
Future use 60ns 68ns 72ns 75ns
*1
*1
42
*1
*1 1
43 44
12ns*
0.45ns 0.5ns
*1
*1
45
0.55ns 0.75ns
*1
*1
46 to 61 62 63
Future use
64 to 65 66 67 to 71 72 73 74 75
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number Module part number Module part number
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
Byte No. Function described 76 77 78 79 80 81 82 83 84 85 86 Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -6B -7A, -7B 87 Module part number -6B, -7B -7A 88 89 90 91 92 93 94 95 to 98 Module part number Module part number Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Bit7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x Bit6 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 1 0 0 0 x x Bit5 1 1 0 0 1 0 0 0 0 1 1 1 0 0 1 0 1 1 1 x x Bit4 1 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 0 1 0 x x Bit3 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 x x Bit2 0 1 1 0 1 0 0 0 0 1 1 1 0 0 1 1 0 0 0 x x Bit1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 x x Bit0 0 0 1 1 0 1 1 1 1 1 0 1 0 1 1 1 0 0 0 x x Hex value 32H 36H 55H 43H 36H 41H 4BH 53H 41H 2DH 36H 37H 42H 41H 2DH 45H 20H 30H 20H xx xx Comments 2 6 U C 6 A K S A -- 6 7 B A -- E (Space) Initial (Space) Year code (HEX) Week code (HEX)
99 to 127 Manufacture specific data
Note:
1. These specifications are defined based on component specification, not module.
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
Block Diagram
/CS1 /CS0 RS DQS0 RS DM0 8 DQ0 to DQ7 RS DQS1 RS DM1 8 DQ8 to DQ15 RS I/O8 to I/O15 I/O8 to I/O15 DQ40 to DQ47 RS I/O0 to I/O7 UDQS UDM I/O0 to I/O7 UDQS UDM DQ32 to DQ39 RS DQS5 RS DM5 8 RS I/O8 to I/O15 RS DQS6 RS LDM 8 DQ16 to DQ23 RS DQS3 RS DM3 8 DQ24 to DQ31 RS I/O8 to I/O15 I/O8 to I/O15 DQ56 to DQ63 RS I/O0 to I/O7 UDQS UDM I/O0 to I/O7 UDQS UDM DQ48 to DQ55 RS DQS7 RS DM7 8 RS I/O8 to I/O15 I/O8 to I/O15 UDM UDM UDQS LDM DM6 8 RS I/O0 to I/O7 I/O0 to I/O7 UDQS LDM LDM LDQS I/O8 to I/O15 UDM UDM UDQS LDM LDM DM4 8 RS I/O0 to I/O7 I/O0 to I/O7 UDQS LDQS RS DQS4 RS LDM LDM LDQS
/CS
LDQS
/CS
/CS
LDQS
/CS
D0
D4
D2
D6
RS DQS2 RS DM2 LDQS
/CS
LDQS
/CS
/CS
LDQS
/CS
D1
D5
D3
D7
* D0 to D7 : 256M bits DDR SDRAM U0 : 2k bits EEPROM Rs : 22 BA0 to BA1 A0 to AN /RAS /CAS /WE CKE0 CKE1 VDDSPD VREF VDD Serial PD SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D3) SDRAMs (D4 to D7) SPD SDRAMs (D0 to D7) SDRAMs (D0 to D7), VDD and VDDQ CK0 /CK0 CK1 /CK1 CK2 10 pF VSS VDDID Open SDRAMs (D0 to D7), SPD /CK2 Notes : 1. DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. VDDID strap connections: (for memory device VDD, VDDQ) Strap out (open): VDD = VDDQ Strap in (closed): VDD VDDQ 2. The SDA pull-up registor is reguired due to the open-drain/open-collector output. 3. The SCL pull-up registor is recommended, because of the normal SCL lime inactive "high" state. 4 loads 4 loads SCL SA0 SA1 SA2 SCL A0 A1 A2 SDA SDA
U0 WP
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
Logical Clock Net Structure
4DRAM loads DRAM1
120 DIMM connector
DRAM2
DRAM3
DRAM4
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD IO PD TA Tstg Value -1.0 to +3.6 -1.0 to +3.6 50 8 0 to +70 -55 to +125 Unit V V mA W C C 1 Note
Note: 1. DDR SDRAM component specification. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 to +70C) (DDR SDRAM Compoment Specification)
Parameter Supply voltage Symbol VDD, VDDQ VSS Input reference voltage Termination voltage Input high voltage Input low voltage Input voltage level, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input differential voltage, CK and /CK inputs VREF VTT VIH (DC) VIL (DC) VIN (DC) VIX (DC) VID (DC) min. 2.3 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.5 x VDDQ - 0.2V 0.36 typ. 2.5 0 0.50 x VDDQ VREF -- -- -- 0.5 x VDDQ -- max. 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 Unit V V V V V V V 2 3 4 Notes 1
0.5 x VDDQ + 0.2V V VDDQ + 0.6 V 5, 6
Notes: 1. 2. 3. 4. 5. 6.
VDDQ must be lower than or equal to VDD. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to -1.0V for the period shorter than or equal to 5ns. VIN (DC) specifies the allowable DC execution of each differential input. VID (DC) specifies the input differential voltage required for switching. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF - 0.18V if measurement.
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
DC Characteristics 1 (TA = 0 to 70C, VDD = 2.5V 0.2V, VSS = 0V)
Parameter Operating current (ACTV-PRE) Operating current (ACTV-READ-PRE) Idle power down standby current Floating idle standby current Quiet idle standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current Self refresh current Operating current (4 banks interleaving) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B Grade -6B -7A, -7B -6B -7A, -7B max. 1320 1200 1560 1440 48 560 480 480 400 320 880 800 2080 1840 2080 1840 3200 2800 48 3240 2800 Unit mA mA mA mA mA mA mA mA mA mA mA mA Test condition CKE VIH, tRC = tRC (min.) CKE VIH, BL = 4, CL = 2.5, tRC = tRC (min.) CKE VIL Notes 1, 2, 9 1, 2, 5 4
CKE VIH, /CS VIH, 4, 5 DQ, DQS, DM = VREF CKE VIH, /CS VIH, 4, 10 DQ, DQS, DM = VREF CKE VIL CKE VIH, /CS VIH tRAS = tRAS (max.) CKE VIH, BL = 2, CL = 2.5 CKE VIH, BL = 2, CL = 2.5 tRFC = tRFC (min.), Input VIL or VIH Input VDD - 0.2 V Input 0.2 V BL = 4 3 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6
1, 5, 6, 7
Notes. 1. These IDD data are measured under condition that DQ pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one cycle. 6. DQ, DM and DQS transition twice per one cycle. 7. 4 banks active. Only one bank is running at tRC = tRC (min.) 8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general. 9. Command/Address transition once every two clock cycles. 10. Command/Address stable at VIH or VIL.
DC Characteristics 2 (TA = 0 to 70C, VDD, VDDQ = 2.5V 0.2V, VSS = 0V)
Parameter Input leakage current Output leakage current Output high current Output low current Symbol ILI ILO IOH IOL min. -16 -10 -15.2 15.2 max. 16 10 -- -- Unit A A mA mA Test condition VDD VIN VSS VDD VOUT VSS VOUT = 1.95V VOUT = 0.35V 1 1 Note
Note: 1. DDR SDRAM component specification.
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
Pin Capacitance (TA = 25C, VDD = 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data and DQS input/output capacitance Symbol CI1 CI2 CO Pins Address, /RAS, /CAS, /WE CK, /CK, CKE, /CS DQ, DQS, DM max. 45 48 18 Unit pF pF pF Note
AC Characteristics (TA = 0 to +70C, VDD, VDDQ = 2.5V 0.2V, VSS = 0V) (DDR SDRAM Component Specification)
-6B Parameter Clock cycle time (CL = 2) (CL = 2.5) CK high-level width CK low-level width CK half period DQ output access time from CK, /CK DQS output access time from CK, /CK DQS to DQ skew DQ/DQS output hold time from DQS Data hold skew factor Symbol tCK tCK tCH tCL tHP tAC tDQSCK tDQSQ tQH tQHS min. 7.5 6 0.45 0.45 min (tCH, tCL) -0.7 -0.6 -- max. 12 12 0.55 0.55 -- 0.7 0.6 0.45 -7A min. 7.5 7.5 0.45 0.45 min (tCH, tCL) -0.75 -0.75 -- max. 12 12 0.55 0.55 -- 0.75 0.75 0.5 -7B min. 10 7.5 0.45 0.45 min (tCH, tCL) -0.75 -0.75 -- max 12 12 0.55 0.55 -- 0.75 0.75 0.5 Unit ns ns tCK tCK tCK ns ns ns ns ns ns ns tCK tCK ns ns ns ns tCK tCK tCK tCK tCK tCK tCK ns ns ns 8 8 7 9 8 8 7 5, 11 6, 11 2, 11 2, 11 3 Notes 10
tHP - tQHS -- -- -0.7 -0.7 0.9 0.4 0.45 0.45 1.75 0.55 0.7 0.7 1.1 0.6 -- -- -- -- -- 0.6 1.25 -- -- -- -- -- -- --
tHP - tQHS -- -- -0.75 -0.75 0.9 0.4 0.5 0.5 1.75 0 0.25 0.4 0.75 0.2 0.2 0.35 0.35 0.9 0.9 2.2 0.75 0.75 0.75 1.1 0.6 -- -- -- -- -- 0.6 1.25 -- -- -- -- -- -- --
tHP - tQHS -- -- -0.75 -0.75 0.9 0.4 0.5 0.5 1.75 0 0.25 0.4 0.75 0.2 0.2 0.35 0.35 0.9 0.9 2.2 0.75 0.75 0.75 1.1 0.6 -- -- -- -- -- 0.6 1.25 -- -- -- -- -- -- --
Data-out high-impedance time from tHZ CK, /CK Data-out low-impedance time from tLZ CK, /CK Read preamble Read postamble DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width Write preamble setup time Write preamble Write postamble Write command to first DQS latching transition DQS falling edge hold time from CK DQS input high pulse width DQS input low pulse width Address and control input setup time Address and control input pulse width tRPRE tRPST tDS tDH tDIPW
tWPRES 0 tWPRE tWPST tDQSS 0.25 0.4 0.75 0.2 0.2 0.35 0.35 0.75 0.75 2.2
DQS falling edge to CK setup time tDSS tDSH tDQSH tDQSL tIS
Address and control input hold time tIH tIPW
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
-6B Parameter Mode register set command cycle time Active to Precharge command period Active to Active/Auto refresh command period Auto refresh to Active/Auto refresh command period Active to Read/Write delay Precharge to active command period Active to Autoprecharge delay Active to active command period Write recovery time Symbol tMRD tRAS tRC tRFC tRCD tRP tRAP tRRD tWR min. 2 42 60 72 18 18 tRCD min. 12 15 max. -- 120000 -- -- -- -- -- -- -- -7A min. 2 45 67.5 75 20 20 tRCD min. 15 15 max. -- 120000 -- -- -- -- -- -- -- -7B min. 2 45 67.5 75 20 20 tRCD min. 15 15 max -- 120000 -- -- -- -- -- -- -- Unit tCK ns ns ns ns ns ns ns ns tCK tCK s 13 Notes
Auto precharge write recovery and tDAL precharge time Internal write to Read command tWTR delay Average periodic refresh interval tREF
(tWR/tCK)+ -- (tRP/tCK) 1 -- -- 7.8
(tWR/tCK)+ -- (tRP/tCK) 1 -- -- 7.8
(tWR/tCK)+ -- (tRP/tCK) 1 -- -- 7.8
Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions, refer to the corresponding component data sheet. 2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing VTT. 5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving. 6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK. 12. VDD is assumed to be 2.5V 0.2V. VDD power supply variation per cycle expected to be less than 0.4V/400 cycle. 13. tDAL = (tWR/tCK)+(tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For -7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns, tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3) tDAL = 5 clocks
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
Timing Parameter Measured in Clock Cycle for unbuffered DIMM
Number of clock cycle tCK Parameter Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay (CL = 2) (CL = 2.5) Burst stop command to DQ High-Z (CL = 2) (CL = 2.5) Read command to write command delay (to output all data) (CL = 2) (CL = 2.5) Pre-charge command to High-Z (CL = 2) (CL = 2.5) Write command to data in latency Write recovery DM to data in latency Mode register set command cycle time Self refresh exit to non-read command Self refresh exit to read command Power down entry Power down exit to command input Symbol tWPD tRPD tWRD tBSTW tBSTW tBSTZ tBSTZ tRWD tRWD tHZP tHZP tWCD tWR tDMD tMRD tSNR tSRD tPDEN tPDEX 6ns min. 4 + BL/2 BL/2 2 + BL/2 -- 3 -- 2.5 -- 3 + BL/2 -- 2.5 1 3 0 2 12 200 1 1 max. -- -- -- -- -- -- 2.5 -- -- -- 2.5 1 -- 0 -- -- -- 1 -- 7.5ns min. 3 + BL/2 BL/2 2 + BL/2 2 3 2 2.5 2 + BL/2 3 + BL/2 2 2.5 1 2 0 2 10 200 1 1 max. -- -- -- -- -- 2 2.5 -- -- 2 2.5 1 -- 0 -- -- -- 1 -- Unit tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
Pin Functions
CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins) Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY8) is loaded via the A0 to the A8 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. BA0, BA1 (input pin) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL. CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH. DQ (input and output pins) Data are input to and output from these pins. DQS (input and output pin) DQS provide the read data strobes (as output) and the write data strobes (as input).
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
DM (input pins) DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and VREF VDD (power supply pins) 2.5V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 2.5V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected.
Detailed Operation Part and Timing Waveforms
Refer to the EDD2516AKTA-E datasheet (E0502E).
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
Physical Outline
Unit: mm
67.60 63.60
11.55 18.45
3.80
(DATUM -A-)
4x Full R
Component area (Front)
20.0
4.00
31.75
6.00
2.15
11.40 4.20
A
47.40
B
199
1
2.45 4.20
1.50
1.00 0.10
2.45
2
11.40
47.40
200
2.15
R0.50 0.20
R0.50 0.20
2x 1.80
Component area (Back)
4.00 0.10
(DATUM -A-)
2.00 Min.
Detail A
(DATUM -A-)
FULL R
4.00 0.10
Detail B
0.60
1.80 1.00 0.10
0.45 0.03
ECA-TS2-0019-01
Preliminary Data Sheet E0605E10 (Ver. 1.0)
17
0.25 Max
2.55
EBD26UC6AKSA-E
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E0605E10 (Ver. 1.0)
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EBD26UC6AKSA-E
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Preliminary Data Sheet E0605E10 (Ver. 1.0)
19

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